Compilation is too Long Danny Mok Altera HK FAE (amok@altera.com) Copyright 1997 Altera Corporation 2/22/2021P1 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.1 Compilation is too Long Danny Mok Altera HK FAE (dmok@altera.com)
Compilation Time Atera lawpplus llis Copyright 1997 Altera Corporation 2/22/2021P2 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.2 Compilation Time
If you were If you were Altera Software Engineer, what shall you do? Graphic Entry H Graphic Compiler H Graphic processor VHDL Entry VHDL Compiler H VHDL processor Fitting AHDL Entry AHDL Compiler AHDL processor EDIF Entry EDIF Compiler H EDIF processor Need different Processor for different Design Entry Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.3 If you were ◼ If you were Altera Software Engineer, what shall you do ? Graphic Entry Graphic Compiler Fitting VHDL Entry VHDL Compiler Graphic processor VHDL processor AHDL Entry EDIF Entry AHDL Compiler EDIF Compiler AHDL processor EDIF processor Need different Processor for different Design Entry
The other better solution Graphic Entry Graphic Compiler VHDL Entry VHDL Compiler Altera nterna Fitting Datab AHDL Entry AHDL Compiler Structurel EDIF Entry EDIF Compiler /AbsRA 2/22/2021P4 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.4 The Other better solution Graphic Entry Graphic Compiler VHDL Entry VHDL Compiler AHDL Entry EDIF Entry AHDL Compiler EDIF Compiler Altera Internal Database Structure Fitting
Altera Max+Plus ll compiler 口区 Compiler Databas Logi Timing Netlist Builder Synthesizer Partitioner Fitter SNF Assembler Extractor Extractor Stop Convert to Partition your Get the device Altera internal whole design timing parameter Data Base into couple for Real time Structure chips Simulation Involve all different Generate the ogIc kind of Optimize Fit your design Program File om pll within altera to program the e.g. AHDL, e.g. Hierarchy Synthesis device device One-Hot State Machine VHDL, Graphic e.g. SOF, POF Carry/Cascade Chain e.g. Pin lock EDIF Implement in EAB Multi-level Synthesis Copyright 1997 Altera Corporation Clique /AbsRA 2/22/2021P Timing parameter favara
Copyright © 1997 Altera Corporation 2/22/2021 P.5 Altera Max+Plus II Compiler Involve all different kind of Compiler e.g. AHDL, VHDL, Graphic EDIF….. Convert to Altera Internal DataBase Structure Logic Optimize e.g. Hierarchy Synthesis One-Hot State Machine Carry/Cascade Chain Multi-level Synthesis…. Partition your whole design into couple chips Fit your design within Altera device e.g. Pin lock, Implement in EAB Clique, Timing parameter Get the device timing parameter for Real time Simulation Generate the Program File to program the device e.g. SOF, POF