Multiple Clock System Design Danny Mok Altera HK FAE (amok@altera.com) Copyright 1997 Altera Corporation 2/22/2021P1 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.1 Multiple Clock System Design Danny Mok Altera HK FAE (dmok@altera.com)
Example DFF F F F clk1 CLRN CLRN clk2 ClkI and Clk2 are the clock which running at different frequency Copyright 1997 Altera Corporation 2/22/2021P2 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.2 Example Clk1 and Clk2 are the clock which running at different frequency
Timing Analyzer ro Timing Analyzer Registered Performance Clock: clk1(1 paths) Info: One or more paths have been found between registers controlled by different Source:: 1.Q Destination:: 2.Q clocks-can't calculate registered performance for those paths Clock period: 3. 4ns Frequency: 294. 11MHz Start Stop List Paths Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.3 Timing Analyzer
Information from Timing analyzer □区 Registered Performance Clock: clk1(1 paths) cili paths Registered Performance ea Timing analyzer Clock: clk1 (1 paths) Registered performance Source:: 1.0 Clock clk2(1 paths Destination:: 2.0 ource 150 Destination:: 5.0 Clock period. 3. 4n Frequency. 294. 11MHz Clock period: 3. 4ns Frequency: 294.11MH Clock period: 6.6ns equency: 151. MHz Start Stop Start st List Paths Sta Stop List Paths
Copyright © 1997 Altera Corporation 2/22/2021 P.4 Information from Timing Analyzer
Information of clk1 DFF F F F clk1 CLRN CLRN clk2 Registered Performance ClkI can run at max 294. MHZ Clock period: 3. 4ns Frequency: 294.11MH: Copyright 1997 Altera Corporation 2/22/2021P Start SLop List Paths favara
Copyright © 1997 Altera Corporation 2/22/2021 P.5 Information of Clk1 Clk1 can run at max. 294.11MHz