Usage of FloorPlanner Danny Mok Altera HK FAE (amok@altera.com) Copyright 1997 Altera Corporation 2/22/2021P1 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.1 Usage of FloorPlanner Danny Mok Altera HK FAE (dmok@altera.com)
What is the Floorplan a It is use to control the placement of your design logic to increase the performance of your design to reduce the rowicolumn traffic resolve the "can not fit issue(Altera Expert can do this for ou use to control the trace delay a Logic Plan can not help you to simplify your design from a Complex to a Simple one Copyright 1997 Altera Corporation 2/22/2021P2 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.2 What is the Floorplan ◼ It is use to control the placement of your design logic – to increase the performance of your design – to reduce the ROW/COLUMN traffic – resolve the “can not fit” issue (Altera Expert can do this for you) – use to control the trace delay ◼ Logic Plan can not help you to simplify your design from a Complex to a Simple one
Why the Floorplan is so important The delay is a combinational of Two Factors Gate delay Trace Delay Two situation to consider Gate Delay >>> Trace Delay(floorplan is useless, logic complexity is more important Gate Delay <<< Trace Delay(floorplan is very important) a For Altera Device, Trace Delay is bigger than Gate Delay, so floorplan is important Trace dela Gate Delay at Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.3 Why the Floorplan is so important ◼ The Delay is a combinational of Two Factors – Gate Delay – Trace Delay ◼ Two situation to consider – Gate Delay >>>> Trace Delay (floorplan is useless, logic complexity is more important) – Gate Delay <<<< Trace Delay (floorplan is very important) ◼ For Altera Device, Trace Delay is bigger than Gate Delay, so floorplan is important Trace Delay Gate Delay
Example 1 at &a ti □回区 Delay Matrix Destinati cell-1-out Icell-2-out 2. 4ns Copyright 1997 Altera Corporation Start List Paths 2/22/2021P4 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.4 Example 1
Example 2 11.7-2. 4=9. 3ns delay caused by TRACE delay Timing Analyzer 口区 Delay matrix Destination Icell-l-out Icell-2-out 7. 2ns 18.ns Icell-1 rIcell-2-out Start Stop List Path Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.5 Example 2 11.7 - 2.4 = 9.3ns delay caused by TRACE DELAY