FPGA Express RESS FPGA Alan ma Senior Corporate Applications Engineer downloadfrom:http://wwwfpga.com.cn @2000 Synops ys, Inc (FE. SynoPSys
© 2000 Synopsys, Inc. (FE.1) FPGA Express Alan Ma Senior Corporate Applications Engineer download from: http://www.fpga.com.cn
Agenda Whatis FPGA Express? Design Flow Design Analysis FPGA Scripting Tool(FST) Summary Verilog Coding Styles Tips Tricks @2000 Synops ys, Inc(FE.2) SynoPSys
© 2000 Synopsys, Inc. (FE.2) Agenda What is FPGA Express? Design Flow Design Analysis FPGA Scripting Tool (FST) Summary Verilog Coding Styles Tips & Tricks
Agenda What is FPGA Express? Design Flow Design analysis FPGA Scripting Tool(fST) Summary Verilog Coding Styles Tips tricks @2000 Synopsys, Inc(FE 3 SynoPSys
© 2000 Synopsys, Inc. (FE.3) Agenda What is FPGA Express? Design Flow Design Analysis FPGA Scripting Tool (FST) Summary Verilog Coding Styles Tips & Tricks
Introduction FPGA Express(Fe) is a powerful synthesis tool for leading FPga and pld architectures The oeM version for altera is tailored to altera architectures: Architecture-specific mapping and optimization Industry-leading quality of results(Qor) Tight integration with Quartus Support for industry-standard verilog and VhDl Easy-to-use design flows and graphical user interfaces Integrated static timing analysis with Time Tracker Vista(visual tools for analysis) including schematic viewing with tight links to Time Tracker TCL-based language for scripting @2000 Synops ys, Inc(FE. 4) SynoPSys
© 2000 Synopsys, Inc. (FE.4) FPGA Express (FE) is a powerful synthesis tool for leading FPGA and PLD architectures The OEM version for Altera is tailored to Altera architectures: Architecture-specific mapping and optimization Industry-leading quality of results (QoR) Tight integration with Quartus Support for industry-standard Verilog and VHDL Easy-to-use design flows and graphical user interfaces Integrated static timing analysis with TimeTracker Vista (visual tools for analysis) including schematic viewing with tight links to TimeTracker TCL-based language for scripting Introduction
State of the Art Synthesis Architecture Specific Mapping ATOMS (O, LCELL), Carry Chains, Cascade Chains Register duplication Supports Mega Wizard Components: LPMS, CAMS, LVDSS, PLLS LPM Inference Arithmetic lpms are inferred for max devices Multiplier LPMs are inferred for ACex, APEX, and flex devices Other arithmetic operators are implemented using atoms Automatic Global Signal Mapping Glo bal Clocks Glo bal resets @2000 Synops ys, Inc(FE.5) SynoPSys
© 2000 Synopsys, Inc. (FE.5) Architecture Specific Mapping ATOMs (IO, LCELL), Carry Chains, Cascade Chains Register Duplication Supports MegaWizard Components: LPMs, CAMs, LVDSs, PLLs LPM Inference Arithmetic LPMs are inferred for MAX devices Multiplier LPMs are inferred for ACEX, APEX, and FLEX devices Other arithmetic operators are implemented using ATOMs Automatic Global Signal Mapping Global Clocks, Global Resets State of the Art Synthesis