Asynchronous vs Synchronous Circuit Design Danny Mok Altera HK FAE (amok@altera.com) bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Asynchronous vs Synchronous Circuit Design Danny Mok Altera HK FAE (dmok@altera.com)
Asynchronous Circuit Design a Mainly use Combinational Logic to do the decoding Address decoder Fifo/Ram Read or Write pulse a The output logic does not have any relationship with any clocking signal a Usually the Decoding Glitch can be monitored at the output signal Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Asynchronous Circuit Design ◼ Mainly use Combinational Logic to do the decoding – Address decoder – Fifo/Ram Read or Write pulse ◼ The output logic does not have any relationship with any clocking signal ◼ Usually the Decoding Glitch can be monitored at the output signal
Synchronous circuit Design a Usually the circuit design will involve with different kind of flip-Flop D type, JK type, Rs type or T type a The output logic is fully control by the rising edge or falling edge of the same clocking signal ■ No Glitch wil‖ be experienced at the output signal Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Synchronous Circuit Design ◼ Usually the circuit design will involve with different kind of Flip-Flop – D type, JK type, RS type or T type ◼ The output logic is fully control by the rising edge or falling edge of the same clocking signal ◼ No Glitch will be experienced at the output signal
Asynchronous Design Example u↑pu 7439go LCLKB LQD cla 1CLKA IQc OUTPUT O2N O3N 日 C OSN On On b BCDTO DEC Binary counter: LLLL LLLH bCd to dec. LllL-> HHHHHHHHHL LLHL LLLH-> HHHHHHHHLH LLHH LLHL→> HHHHHHHLHE LLHH->HHHHHHLHHH HHHE Copyright 1997 Altera Corporation HLLH->LHHHHHHHHH 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Asynchronous Design Example Binary Counter : LLLL LLLH LLHL LLHH .......... HHHH BCD to DEC : LLLL -> HHHHHHHHHL LLLH -> HHHHHHHHLH LLHL -> HHHHHHHLHH LLHH -> HHHHHHLHHH .......... -> ............................ HLLH -> LHHHHHHHHH
Expect Output Start: 0.Ons ]□」End「1us Interval: 1. Ous ‖Name Value 100 Ons 200.ns 300 Ons 400 Ons 500. Ons 0000 This is the dLE output waveform but what will we get really? bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Expect Output This is the IDLE output waveform but what will we get really ?