Push-Button mode Place-and-Route in Quartus Right-click an optimized chip and select"Place and route chip FEgenerates. edf, Imf, tcl files and launches Quartus in the background Available only when targeting APEX20K/E FPGA Express-[demo. expl s Eile Edit Synthesis Script Filters yiew window Help 8国(m ? To generate a netlist for place route, select the optimized chip land then choose Export Netlist Design Sources 日 o demo +)- micro (Altera-APEX20K AUTOFASTEST 日-woRK 帝血 o-Optimized (Altera APEX2 K: AUTOFASTEST 中- tim hier. vhd View Results sr micro, wh Update Chip orce Update Chip +1-B convsegs whd Optimize Chs Place and route Chip Export FPGA Scrip KKDMIN Errors AA Messages/ Chip Report For Help, press F1 Delete Chip @2000 Synops ys, Inc(FE. 16) SynoPSys
© 2000 Synopsys, Inc. (FE.16) Right-click an optimized chip and select “Place and Route Chip” FE generates .edf, .lmf, .tcl files and launches Quartus in the background Available only when targeting APEX20K/E Push-Button Mode Place-and-Route in Quartus
Push-Button mode Place-and-Route in MaXtplus Right-click an optimized chip and select"Export Netlist Use the export directory as the max+plus lI project directory 口区 略早 Export Netlist Basename of files: micro CA micro (Altera-FLEX1OK AUTOFASTEST E.*micto-Optimized (Altera-FLEX1OKAUTOFASTEST. Export Directory. c: \projects \demo\outputs View Results Place and Route Output Format: NONE Update Chip Export Timing Specifications Force Update Chip Bus Style: EXPAND Synopsys Design Database Optimize Ch I Generate Synopsys do files Place and Flout Crip Export FPGA Script Chip report Delete Chip Del @2000 Synops ys, Inc(FE.17) SynoPSys
© 2000 Synopsys, Inc. (FE.17) Right-click an optimized chip and select “Export Netlist” Use the export directory as the MAX+plus II project directory Push-Button Mode Place-and-Route in MAX+plus II
Constraint mode More control on synthesis and place-and-route results Create project Add source files(analyze Select target device( Create Implementation) Enter Constraints Optimize Place-and-Route in Quartus(Export Netlist and then Place-and-Route in MAX+plus D) @2000 Synops ys, Inc(FE. 18) SynoPSys
© 2000 Synopsys, Inc. (FE.18) More control on synthesis and place-and-route results Create Project Add source files (Analyze) Select target device (Create Implementation) Enter Constraints Optimize Place-and-Route in Quartus (Export Netlist and then Place-and-Route in MAX+plus II) Constraint Mode
Constraint mode edit constraints Skip constraint entry during create implementation Create Implementation-micro 区 Implementation Name micro ne from tH 4 Target device w desigr display Vendor Device AUTO Effort Speed grade APEX20K FASTEST V Preserve Hierarchy Clock frequency Do not insert I /0 pads Unchecked the box to create elaborated chip only 厂 Skip constraint entry OK Cancel @2000 Synops ys, Inc(FE. 19) SynoPSys
© 2000 Synopsys, Inc. (FE.19) Skip constraint entry during create implementation Constraint Mode Edit Constraints Unchecked the box to create elaborated chip only
Constraint mode edit constraints Right-click an elaborated chip and select"Edit Constraints N Ele Edit Synthesis Script Fiters yiew window Help 品 命心? Right click on chip to Edit Constraints (optional] and Optimize 日飞demo B)-K micro (Altera- APEX20K: AUTOFASTEST) 日已wRK +- tim _ hier.vhd View Schematic Update Chip Force Update Ch b micro_st. hd Optimize Chip Place and Foute Chip x Warning: Clock signal is not in the sensitivity list. Export FPGA Script. in routine counter line 15 in file D:/temp/del Export DC Script (HDL-400) Chip report ADPN Errors入 Warnings人Mes09s3 Delete Chip @2000 Synops ys, Inc(FE.20) SynoPSys
© 2000 Synopsys, Inc. (FE.20) Right-click an elaborated chip and select “Edit Constraints” Constraint Mode Edit Constraints