Push-Button mode Create Project Specify a name for the project FEcreates a directory of that name to save project .exp) and intermediate files File View Help 8启 FPGA Express prc Create new FPGA Express project 合 Projects 画国 Name Create 风 ADDINErrors/ Warnings入 Messages/ reate a new FPGA Express Project @2000 Synops ys, Inc(FE. 11) SynoPSys
© 2000 Synopsys, Inc. (FE.11) Specify a name for the project FE creates a directory of that name to save project (*.exp) and intermediate files Push-Button Mode Create Project
Push-Button mode Analyze Add Source Files(analyze Drag and drop source files (edie, verilog, VHDL) into Design Sources window Errors and warnings are identified in the Output window S FPGA Express-[demo.exp] 口区 s- Eile Edt Synthesis Script Filters yiew Window Help 口②回 D counter 4 >物岭 FPGA Express automatically analyzes HDL source files as they are added Use the errors/warnings viewer to help correct any syntax errors 回 Design Sources Chips File Edit View Help 日w0RK -EY tim_hier. hd B counter 4.vhd 中 display. vhd convsegsvhd whd display, whd micro whd 由& micro st yhd xIError: D: /temp/designs/tim hier. vhd line 53 micro yhd micro st yhd tim hier yhd Syntax error -unexpected end of input. (VSS-1081 6 object(s 989KB KKDMErrors A Warnings A Messages For Help, press F1 @2000 Synops ys, Inc (FE. 12) SynoPSys
© 2000 Synopsys, Inc. (FE.12) Add Source Files (Analyze) Drag and drop source files (EDIF, Verilog, VHDL) into Design Sources Window Errors and warnings are identified in the Output Window Push-Button Mode Analyze
Push-Button mode Analyze: Debugging Double-clicking on the error message shows the errorsource .=file has been modified,!= warnings, X=errors _口区 Eile Edit Synthesis Script Filters View window Help 的@品 咖? F4 and Shift-F4 show next (previous]errors, and move the cursor to the indicated line Right click in editor window for popup menu of commands sdemo es 回x图 demo.exp-tim_hierwhd[HDLEditorl 口区 Design Sources 52 end process 日woRK 53 end SYsTEM Missing EEx tim_hier t-b counter. hd Error: D: /temp/designs/tim hier. vhd line 53 A micro yhd Syntax error -unexpected end of input R XError: D: /temp/ designs/tim hier. vhd line53 Syntax error unexpected end of input. (VSS-108 KDDIMErrors A Warnings A Messages For Help, press F1 @2000 Synops ys, Inc(FE.13 SynoPSys
© 2000 Synopsys, Inc. (FE.13) Double-clicking on the error message shows the error source ? = file has been modified, ! = warnings, X = errors Push-Button Mode Analyze: Debugging Missing ;
Push-Button mode Create Implementation optimize Select Target Device(Create Implementation) Select the top level module from the Tool Bar Specify family, device, speed grade, clock frequency, etc from the Create Implementation dialog box Select"Skip constraint entry"to optimize without additional constraints Create Implementation-micro mplementation Name micro Target device- Optimize for Vendor Device c Speed micro st on'vseas Effort o High V Preserve Hierarchy Clock frequency 50 d Do not insert 1/0 pads V Skip constraint entry Cancel Hel @2000 Synops ys, Inc(FE. 14) SynoPSys
© 2000 Synopsys, Inc. (FE.14) Select Target Device (Create Implementation) Select the top level module from the Tool Bar Specify family, device, speed grade, clock frequency, etc. from the Create Implementation dialog box Select “Skip constraint entry” to optimize without additional constraints Push-Button Mode Create Implementation & Optimize
Push-Button mode Create Implementation optimize Optimize FEmaps to Altera-specific primitives Automatically done in push-button mode skip constraint entry checked) S FPGA Express-[demo.exp] 口区 s- Eile Edt Synthesis Script Filters yiew Window Help 口②回 品「m地 >物岭 To synthesize the design, select the top level design name from the drop down list Then choose the target FPGa device to synthesize a new design implementation Design Sources I chip demo t-k micro (Altera APEX20K: AUTOFASTEST Elaborated 日wDRK # micro-Optimized (Altera-APEX20K: AUTOFASTEST Optimized +- tim_ hier. vhd B counter 4.vhd micro whd 由& micro st yhd KKDMErrors A Warnings A Messages For Help, press F1 @2000 Synops ys, Inc(FE. 15 SynoPSys
© 2000 Synopsys, Inc. (FE.15) Optimize FE maps to Altera-specific primitives Automatically done in push-button mode (Skip constraint entry checked) Push-Button Mode Create Implementation & Optimize Elaborated Optimized