电子种越女学 University of Electroale Science and Technelery of China 986 Chapter 6 Folding Dr.Ling National Key Lab of Science and Technology on Communications
Chapter 6 Folding Dr. Ling National Key Lab of Science and Technology on Communications
Folding /96 The folding transformation is used to systematically determine the control circuits in DSP architectures where multiple algorithm operations are time- multiplexed to a single function unit. ■ By executing multiple algorithm operations on a signal functional unit,the number of functional units in the implementation is reduced,resulting in an integrated circuits with low silicon area. It is important to minimize the silicon area of the IC, which is achieved by reducing the number of functional units,registers,multiplex and interconnection wires. 2021年2月 2
2021年2月 2 Folding The folding transformation is used to systematically determine the control circuits in DSP architectures where multiple algorithm operations are timemultiplexed to a single function unit. By executing multiple algorithm operations on a signal functional unit, the number of functional units in the implementation is reduced, resulting in an integrated circuits with low silicon area. It is important to minimize the silicon area of the IC, which is achieved by reducing the number of functional units, registers, multiplex and interconnection wires
6.1 introduction 956 y(n)=a(n)+b(n)+c(n) 21+0 b(n)· 21+1 (n) b(n) c(n) a(n) <21+0 21+0/ y(n) a(n) →y(n) (1) (1) T2+1 Cycle Adder input Adder input Output (left) (top) 0 a(0) b(0) 1 a(0)+b(0) c(0) 2 a(1) b(1) a(0)+b(0)+c(0) 3 a(1)+b(1) c(1) 4 a(2) b(2) a(1)+b(1)+c(1) 5 a(2)+b(2) c(2) 2021年2月 3
2021年2月 3 6.1 introduction a(n) + + y(n) b(n) c(n) (1) (1) + D a(n) b(n) c(n) y(n) 2l+0 2l+1 2l+0 2l+0 2l+1 y(n) a(n) b(n) c(n) Cycle Adder input (left) Adder input (top) Output 0 a(0) b(0) 1 a(0)+b(0) c(0) 2 a(1) b(1) a(0)+b(0)+c(0) 3 a(1)+b(1) c(1) 4 a(2) b(2) a(1)+b(1)+c(1) 5 a(2)+b(2) c(2)
/96 In general,the data on the input of the folded realization is assumed to be valid for N cycles before changing,where N is the number of algorithm operations executed on a single functional unit in hardware. Folding provides a means for trading area for time in a DSP architecture. Folding can be used to reduce the number of hardware functional units by a factor of N at the expense of increasing the computation frequency by a factor of N. 2021年2月 4
2021年2月 4 In general, the data on the input of the folded realization is assumed to be valid for N cycles before changing, where N is the number of algorithm operations executed on a single functional unit in hardware. Folding provides a means for trading area for time in a DSP architecture. Folding can be used to reduce the number of hardware functional units by a factor of N at the expense of increasing the computation frequency by a factor of N
/96 While the folding transformation reduces the number of functional units in the architecture,it may also lead to an architecture that uses a large amount of registers. To avoid architectures using excessive amounts of registers,techniques can be used to compute the minimum number of registers and to allocation data to these register. 2021年2月 5
2021年2月 5 While the folding transformation reduces the number of functional units in the architecture, it may also lead to an architecture that uses a large amount of registers. To avoid architectures using excessive amounts of registers, techniques can be used to compute the minimum number of registers and to allocation data to these register