Modelsim libraries Directories that contain compiled design units Both VHDL and Verilog are compiled into libraries Two Types Working(default work) Contains the current design unit being compiled Must create a working library before compiling Only one allowed per compilation Resource Contains designs units that can be referenced by the current compilation Multiple allowed during compilation VHDL libraries can be referenced by library and Use clauses
16 ModelSim Libraries ◼ Directories that contain compiled design units – Both VHDL and Verilog are compiled into libraries ◼ Two Types – Working (default work) • Contains the current design unit being compiled • Must create a working library before compiling • Only one allowed per compilation – Resource • Contains designs units that can be referenced by the current compilation • Multiple allowed during compilation • VHDL libraries can be referenced by LIBRARY and USE clauses
Modelsim Design Units Primary ■ Secondary Must have a unique name Units in the same library in a given library may use a common name VHDL VHDL Entities Architectures Package Declarations Package bodies Configurations No Verilog secondary units Verilog Modules User defined Primitives
17 ModelSim Design Units ◼ Primary – Must have a unique name in a given library – VHDL • Entities • Package Declarations • Configurations – Verilog • Modules • User Defined Primitives ◼ Secondary – Units in the same library may use a common name – VHDL • Architectures • Package bodies – No Verilog secondary units
VHDL Predefined libraries ■VHDL Library std contains packages standard and textio These packages should not be modified novice users ■| EPUre Contains only IEEE approved std_logic_1164 packages Accelerated for simulation ■|EEE Contains precompiled Synopsys and IeEe arithmetic packages For std logic base type Accelerated for simulation
18 ◼ VHDL – Library std contains packages standard and textio • These packages should not be modified novice users ◼ IEEEpure – Contains only IEEE approved std_logic_1164 packages – Accelerated for simulation ◼ IEEE – Contains precompiled Synopsys and IEEE arithmetic packages – For std_logic base type – Accelerated for simulation VHDL Predefined Libraries
vlib <brary_ name> Command ■ Creates libraries <library_name> ■ Default is work info lock any_ verilog_ module any_ vhdl unit primary.dat primary. dat primaryⅦhd <arch name>. dat verilog asm <arch name>.asm ■ Where primary dat -encoded form of verilog module or VHDL entity primary. vhd -VHDL entity representation of verilog ports <arch name>. dat -encoded form of vhdl architecture verilog. asm and sarch name>. asm-executable code files
19 vlib <library_name> Command ◼ Creates libraries ◼ Default is work <library_name> _info any_verilog_module any_vhdl_unit _lock _primary.dat _primary.vhd verilog.asm _primary.dat <arch_name>.dat <arch_name>.asm ◼ Where – _primary.dat - encoded form of Verilog module or VHDL entity – _primary.vhd - VHDL entity representation of Verilog ports – <arch_name>.dat - encoded form of VHDL architecture – verilog.asm and <arch_name>.asm - executable code files
Creating Libraries(Ul) delSim ALTERA 5. 3d Altera Edit Design View Run Macro Options Window Help 国到 Browse Libraries eate a New Library ModelSim> View Library Contents. Compile Project : Create a New Library 口区 Load New Design. Create Select a new library End Simulation. C anew library and a logical mapping to it on/y and type library c a new library only (no mapping name C a map to an existing library This command creates a Browse library subdirectory in the local directory vib lpm sim
20 Creating Libraries (UI) Select a new library only and type library name This command creates a library subdirectory in the local directory -> vlib lpm_sim