Dewey, A " Digital and Analog Electronic Design Automation The Electrical Engineering Handbook Ed. Richard C. Dorf Boca raton crc Press llc. 2000
Dewey, A. “Digital and Analog Electronic Design Automation” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000
34 Digital and analog Electronic Design Automation 34.1 Introduction 34.2 Design Entry ming Analysis. Simulation. Analog Simulation. Emulation 34.6 Test Allen Dewey Fault Modeling.Fault Testing Duke University 34.1 Introduction The field of design automation(DA)technology, also commonly called computer-aided design(CAD)or mputer-aided engineering(CAE), involves developing computer programs to conduct portions of product design and manufacturing on behalf of the designer. Competitive pressures to produce more efficiently new generations of products having improved function and performance are motivating the growing importance of DA. The increasing complexities of microelectronic technology, shown in Fig 34. 1, illustrate the importance of relegating portions of product development to computer automation [Barbe, 1980] Advances in microelectronic technology enable over 1 million devices to be manufactured on an integrated circuit that is smaller than a postage stamp; yet the ability to exploit this capability remains a challenge. Manual design techniques are unable to keep pace with product design cycle demands and are being replaced by automated design techniques [ Saprio, 1986; Dillinger, 1988] Figure 34.2 rizes the historical development of DA technology. DA computer programs are often imply called applications or tools. DA efforts started in the early 1960s as academic research projects and captive industrial programs; these efforts focused on tools for physical and logical design. Follow-on developments extended logic simulation to more-detailed circuit and device simulation and more-abstract functional simula tion. Starting in the mid to late 1970s, new areas of test and synthesis emerged and vendors started offering commercial DA products. Today, the electronic design automation(EDA)industry is an international business with a well-established and expanding technical base [Trimberger, 1990]. EDA will be examined by presenting an overview of the following area Verification Physical design, and c 2000 by CRC Press LLC
© 2000 by CRC Press LLC 34 Digital and Analog Electronic Design Automation 34.1 Introduction 34.2 Design Entry 34.3 Synthesis 34.4 Verification Timing Analysis • Simulation • Analog Simulation • Emulation 34.5 Physical Design 34.6 Test Fault Modeling • Fault Testing 34.7 Summary 34.1 Introduction The field of design automation (DA) technology, also commonly called computer-aided design (CAD) or computer-aided engineering (CAE), involves developing computer programs to conduct portions of product design and manufacturing on behalf of the designer. Competitive pressures to produce more efficiently new generations of products having improved function and performance are motivating the growing importance of DA. The increasing complexities of microelectronic technology, shown in Fig. 34.1, illustrate the importance of relegating portions of product development to computer automation [Barbe, 1980]. Advances in microelectronic technology enable over 1 million devices to be manufactured on an integrated circuit that is smaller than a postage stamp; yet the ability to exploit this capability remains a challenge. Manual design techniques are unable to keep pace with product design cycle demands and are being replaced by automated design techniques [Saprio, 1986; Dillinger, 1988]. Figure 34.2 summarizes the historical development of DA technology. DA computer programs are often simply called applications or tools. DA efforts started in the early 1960s as academic research projects and captive industrial programs; these efforts focused on tools for physical and logical design. Follow-on developments extended logic simulation to more-detailed circuit and device simulation and more-abstract functional simulation. Starting in the mid to late 1970s, new areas of test and synthesis emerged and vendors started offering commercial DA products. Today, the electronic design automation (EDA) industry is an international business with a well-established and expanding technical base [Trimberger, 1990]. EDA will be examined by presenting an overview of the following areas: • Design entry, • Synthesis, • Verification, • Physical design, and • Test. Allen Dewey Duke University
Frequency VLSI 1960 1970 Medium Scale Inte LSI- Large Scale Integration FIGURE 34.1 Microelectronic technology complexity. Circuit devic High-Level Design NMOS Methodology AIT FIGURE 34.2 DA technology development. 34.2 Design Entry Design entry, also called design capture, is the process of communicating with a DA system. In short, design entry is how an engineer"talks"to a DA application and/or system. ny sort of communication is composed of two elements: language and mechanism. Language provides common semantics; mechanism provides a means by which to convey the common semantics. For example, people communicate via a language, such as English or German, and a mechanism, such as a telephone or electronic mail For design, a digital system can be described in many ways, involving different perspectives or abstractions. An abstraction defines at a particular level of detail the behavior or semantics of a digital system, i.e., how the outputs respond to the inputs. Fig 34.3 illustrates several popular levels of abstractions. Moving from the lower left to the upper right, the level of abstraction generally increases, meaning that physical models are the most detailed and specification models are the least detailed. The trend toward higher levels of desig entry abstraction supports the need to address greater levels of complexity [Peterson, 1981 The physical level of abstraction involves geometric information that defines electrical devices and their interconnection. Geometric information includes the shape jects and how objects are placed relative te each other. For example, Fig 34. 4 shows the geometric shapes defining a simple complementary metal-oxide semiconductor(CMOS)inverter. The shapes denote different materials, such as aluminum and polysilicon, and connections, called contacts or vias. c 2000 by CRC Press LLC
© 2000 by CRC Press LLC 34.2 Design Entry Design entry, also called design capture, is the process of communicating with a DA system. In short, design entry is how an engineer “talks” to a DA application and/or system. Any sort of communication is composed of two elements: language and mechanism. Language provides common semantics; mechanism provides a means by which to convey the common semantics. For example, people communicate via a language, such as English or German, and a mechanism, such as a telephone or electronic mail. For design, a digital system can be described in many ways, involving different perspectives or abstractions. An abstraction defines at a particular level of detail the behavior or semantics of a digital system, i.e., how the outputs respond to the inputs. Fig. 34.3 illustrates several popular levels of abstractions. Moving from the lower left to the upper right, the level of abstraction generally increases, meaning that physical models are the most detailed and specification models are the least detailed. The trend toward higher levels of design entry abstraction supports the need to address greater levels of complexity [Peterson, 1981]. The physical level of abstraction involves geometric information that defines electrical devices and their interconnection. Geometric information includes the shape of objects and how objects are placed relative to each other. For example, Fig. 34.4 shows the geometric shapes defining a simple complementary metal-oxide semiconductor (CMOS) inverter. The shapes denote different materials, such as aluminum and polysilicon, and connections, called contacts or vias. FIGURE 34.1 Microelectronic technology complexity. FIGURE 34.2 DA technology development
Time Gates architectural FIGURE 34.3 DA abstractions Design entry mechanisms for physical tual and graphical techniques. With textual techniques, geometric hape and placement are described via an artwork description language, such as Caltech Intermediate Form( CIF)or Electronic Design Intermediate Form(EDIF). With graphical techniques, Silicon geometric shape and placement are described by rendering the objects on a display terminal. The electrical level abstracts physical information into corre- ponding electrical devices, such as capacitors, transistors, and FIGURE 34.4 Physical abstraction. resistors. Electrical information includes device behavior in terms of terminal current and voltage relationships. Device behavior may also be defined in terms of manu facturing parameters. Fig 34.5 shows the electrical symbols denoting a CMOS inverter. The logical level abstracts electrical information into corresponding logical elements, such as and gates,or gates,and inverters. Logical information includes truth table and/or characteristic-switching algebra equations and active-level designations. Fig 34.6 shows the logical symbol for a CMOS inverter. Notice how the amount of information decreases as the level of abstraction increases FIGURE 34.5 Electrical abstraction FIGURE 34.6 Logical abstraction c 2000 by CRC Press LLC
© 2000 by CRC Press LLC Design entry mechanisms for physical information involve textual and graphical techniques.With textual techniques, geometric shape and placement are described via an artwork description language, such as Caltech Intermediate Form (CIF) or Electronic Design Intermediate Form (EDIF). With graphical techniques, geometric shape and placement are described by rendering the objects on a display terminal. The electrical level abstracts physical information into corresponding electrical devices, such as capacitors, transistors, and resistors. Electrical information includes device behavior in terms of terminal current and voltage relationships. Device behavior may also be defined in terms of manufacturing parameters. Fig. 34.5 shows the electrical symbols denoting a CMOS inverter. The logical level abstracts electrical information into corresponding logical elements, such as and gates, or gates, and inverters. Logical information includes truth table and/or characteristic-switching algebra equations and active-level designations. Fig. 34.6 shows the logical symbol for a CMOS inverter. Notice how the amount of information decreases as the level of abstraction increases. FIGURE 34.3 DA abstractions. FIGURE 34.5 Electrical abstraction. FIGURE 34.6 Logical abstraction. FIGURE 34.4 Physical abstraction
Digital System Block Diagram FIGURE 34.7 State diagram. Design entry mechanisms for electrical and logical abstractions are collectively called schematic cap chniques. Schematic capture defines hierarchical structures, commonly called netlists, of components. A designer creates instances of components supplied from a library of predefined components and connects component pins or ports via wires [Douglas-Young, 1988; Pechet 1991 The functional level abstracts logical elements into corresponding computational units, such as registers, multiplexers, and arithmetic logic units(ALUs). The architectural level abstracts functional information into computational algorithms or paradigms. Examples of common computational paradigms are listed below State diagrams Petri nets, Control/data flow graphs, Function tables sion diagrams. These higher levels of abstraction support a more expressive, higher-bandwidth"communication interface between engineers and DA programs. Engineers can focus their creative, cognitive skills on concept and ehavior, rather than on the complexities of detailed implementation. Associated design entry mechanisms typically use hardware description languages with a combination of textual and graphic techniques [ Birtwistle and Subrahmanyan, 1988] Figure 34.7 shows an example of a simple state diagram. The state diagram defines three states, denoted by circles. State-to-state transitions are denoted by labeled arcs; state transitions depend on the present state and the input X. The output, Z, per state is given within each state. Since the output is dependent on only the present state, the digital system is classified as a Moore finite state machine. If the output is dependent on the present state and input, then the digital system is classified as a Mealy finite state machine A hardware description language model written in VHDL of the Moore finite state machine is given in Fig. 34.8. The VHDL model, called a design entity, uses a"data flow"description style to describe the state machine[Dewey, 1983, 1992, 1997]. The entity statement defines the interface, i. e, the ports. The ports include two input signals, X and CLK, and an output signal Z. The ports are of type BiT, which specifies that the signals may only carry the values 0 or 1. The architecture statement defines the input/output transform via two concurrent signal assignment statements. The internal signal STATE holds the finite state information and is driven by a guarded, conditional concurrent signal assignment statement that executes when the associated (CLK='I and not CLKSTABLE is true, which is only on the rising edge of the signal CLK STABLE is a predefined attribute of the signal CLK CLK'STABLE is true if CLK has not changed value. Thus, if"not CLK'STABLE" is true, meaning that CLK has
© 2000 by CRC Press LLC Design entry mechanisms for electrical and logical abstractions are collectively called schematic capture techniques. Schematic capture defines hierarchical structures, commonly called netlists, of components. A designer creates instances of components supplied from a library of predefined components and connects component pins or ports via wires [Douglas-Young, 1988; Pechet, 1991]. The functional level abstracts logical elements into corresponding computational units, such as registers, multiplexers, and arithmetic logic units (ALUs). The architectural level abstracts functional information into computational algorithms or paradigms. Examples of common computational paradigms are listed below: • State diagrams, • Petri nets, • Control/data flow graphs, • Function tables, • Spreadsheets, and • Binary decision diagrams. These higher levels of abstraction support a more expressive, “higher-bandwidth” communication interface between engineers and DA programs. Engineers can focus their creative, cognitive skills on concept and behavior, rather than on the complexities of detailed implementation. Associated design entry mechanisms typically use hardware description languages with a combination of textual and graphic techniques [Birtwistle and Subrahmanyan, 1988]. Figure 34.7 shows an example of a simple state diagram. The state diagram defines three states, denoted by circles. State-to-state transitions are denoted by labeled arcs; state transitions depend on the present state and the input X. The output, Z, per state is given within each state. Since the output is dependent on only the present state, the digital system is classified as a Moore finite state machine. If the output is dependent on the present state and input, then the digital system is classified as a Mealy finite state machine. A hardware description language model written in VHDL of the Moore finite state machine is given in Fig. 34.8. The VHDL model, called a design entity, uses a “data flow” description style to describe the state machine [Dewey, 1983, 1992, 1997]. The entity statement defines the interface, i.e., the ports. The ports include two input signals, X and CLK, and an output signal Z. The ports are of type BIT, which specifies that the signals may only carry the values 0 or 1. The architecture statement defines the input/output transform via two concurrent signal assignment statements. The internal signal STATE holds the finite state information and is driven by a guarded, conditional concurrent signal assignment statement that executes when the associated block expression (CLK=’1’ and not CLK’STABLE) is true, which is only on the rising edge of the signal CLK. STABLE is a predefined attribute of the signal CLK; CLK’STABLE is true if CLK has not changed value. Thus, if “not CLK’STABLE” is true, meaning that CLK has FIGURE 34.7 State diagram