Carpenter, G.L., Choma, Jr,J. Amplifiers The Electrical Engineering Handbook Ed. Richard C. Dorf Boca raton crc Press llc. 2000
Carpenter, G.L., Choma, Jr., J. “Amplifiers” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000
28 amplifiers DC Operating Point. Graphical Approach.Power Amplifiers Gordon L. Carpenter 8.2 Small Signal Analysis Hybrid-Pi Equivalent Circuit. Hybrid-Pi Equivalent Circuit of a MonolithicBt.commOnEmitterAmplifier.design hn Choma, ]r Considerations for the Common Emitter Amplifier. Common Base Amplifier. Design Considerations for the Common Base University of Southern california Amplifier.commonCollectorAmplifier 28.1 Large Signal Analysis Gordon L. Carpenter Large signal amplifiers are usually confined to using bipolar transistors as their solid state devices because of the large linear region of amplification required. One exception to this is the use of VMOS for large por outputs due to their ability to have a large linear region. There are three basic configurations of amplifiers common emitter(CE)amplifiers, common base(CB)amplifiers, and common collection(CC)amplifiers. The basic configuration of each is shown in Fig. 28.1 In an amplifier system, the last stage of a voltage amplifier string has to be considered as a large signal amplifier, and generally EF amplifiers are used as large signal amplifiers. This then requires that the dc bias or dc operating point (quiescent point) be located near the center of the load line in order to get the maximum output voltage swing. Small signal analysis can be used to evaluate the amplifier for voltage gain, current gain, input impedance, and output impedance, all of which are discussed later. DC Operating Point Each transistor connected in a particular amplifier configuration has a set of characteristic curves, as show When amplifiers are coupled together with capacitors, the configuration is as shown in Fig. 28. 3. The load resistor is really the input im of the next stage. To be able to evaluate this amplifier, a dc equivalent circuit needs to be developed n in Fig. 28.4. This will result in the following dc bias equation Assume h >>1 R where beta(heE) is the current gain of the transistor and vae is the conducting voltage across the base-emitter junction. This equation is the same for all amplifier configurations. Looking at Fig. 28.3, the input circuit can be reduced to the dc circuit shown in Fig. 28.4 using circuit analysis techniques, resulting in the following c 2000 by CRC Press LLC
© 2000 by CRC Press LLC 28 Amplifiers 28.1 Large Signal Analysis DC Operating Point • Graphical Approach • Power Amplifiers 28.2 Small Signal Analysis Hybrid-Pi Equivalent Circuit • Hybrid-Pi Equivalent Circuit of a Monolithic BJT • Common Emitter Amplifier • Design Considerations for the Common Emitter Amplifier • Common Base Amplifier • Design Considerations for the Common Base Amplifier • Common Collector Amplifier 28.1 Large Signal Analysis Gordon L. Carpenter Large signal amplifiers are usually confined to using bipolar transistors as their solid state devices because of the large linear region of amplification required. One exception to this is the use of VMOS for large power outputs due to their ability to have a large linear region. There are three basic configurations of amplifiers: common emitter (CE) amplifiers, common base (CB) amplifiers, and common collection(CC) amplifiers. The basic configuration of each is shown in Fig. 28.1. In an amplifier system, the last stage of a voltage amplifier string has to be considered as a large signal amplifier, and generally EF amplifiers are used as large signal amplifiers. This then requires that the dc bias or dc operating point (quiescent point) be located near the center of the load line in order to get the maximum output voltage swing. Small signal analysis can be used to evaluate the amplifier for voltage gain, current gain, input impedance, and output impedance, all of which are discussed later. DC Operating Point Each transistor connected in a particular amplifier configuration has a set of characteristic curves, as shown in Fig. 28.2. When amplifiers are coupled together with capacitors, the configuration is as shown in Fig. 28.3. The load resistor is really the input impedance of the next stage. To be able to evaluate this amplifier, a dc equivalent circuit needs to be developed as shown in Fig. 28.4. This will result in the following dc bias equation: where beta (hFE) is the current gain of the transistor and VBE is the conducting voltage across the base-emitter junction. This equation is the same for all amplifier configurations. Looking at Fig. 28.3, the input circuit can be reduced to the dc circuit shown in Fig. 28.4 using circuit analysis techniques, resulting in the following equations: I V V R R h CQ BB BE B E FE = - + >> beta Assume 1 Gordon L. Carpenter California State University, Long Beach John Choma, Jr. University of Southern California
Rc RB Re o RE (a)Common en (b)Common collector (c)Common base (emitter follower FIGURE 28. 1 Amplifier circuits. (Source: C J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed, Redwood City, Calif. Benjamin-Cummings, 1991, P 80. With permission. Load line 0.3 0.2(mA) Cutoff res FIGURE 28. 2 Transistor characteristic curves. Source: C J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed, Redwood City, Calif. Benjamin-Cummings, 1991, P. 82. with permission. Rc E R Re RI ie FIGURE 28.3 Amplifier circuit. Source: C ]. Savant, M. FIGURE 28.4 Amplifier equivalent circuit. Source: C ]. oden, and G. Carpenter, Electronic Design, Circuits and Savant, M. Roden, and G. Carpenter, Electronic Design, ystems, 2nd ed, Redwood City, Calif. Benjamin-Cum Circuits and Systems, 2nd ed, Redwood City, Calif. Ben- mings,1991,P. 92. With permission min-Cummings, 1991,P. 82. With permission c 2000 by CRC Press LLC
© 2000 by CRC Press LLC FIGURE 28.1 Amplifier circuits. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 80. With permission.) FIGURE 28.2 Transistor characteristic curves. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 82. With permission.) FIGURE 28.3 Amplifier circuit. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 92. With permission.) FIGURE 28.4 Amplifier equivalent circuit. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 82. With permission.)
VBB= VTH= VCC(RI/(R,+ R2) RB=RTH=rIIR2 or this biasing system, the Thevenin equivalent resistance and the Thevenin equivalent voltage can be deter- mined. For design with the biasing system shown in Fig. 28.3, then R=RB/(l-VBB/VaO R2=RB(Vcc/VE Graphical Approach To understand the graphical approach, a clear understanding of the dc and ac load lines is necessary. The dc load line is based on the Kirchhoffs equation from the dc power source to ground(all capacitors open CC- VCE+ icR DC where roc is the sum of the resistors in the collector-emitter loop The ac load line is the loop, assuming the transistor is the ac source and the source voltage is zero, where Rar is the sum of series resistors in that loop with all the capacitors shorted. The load lines then can be constructed on the characteristic curves as shown in Fig. 28.5. From this it can be seen that to get the maximum output voltage swing, the quiescent point, or Q point, should be located in the middle of the ac load line. To place the Q point in the middle of the ac load line, Ico can be determined from the equation Ioo= vccl(nc +.d) icQ =lc ac load line with slope load line with slope Vce Vcc EQ IGURE 28.5 Load lines. (Source: C J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd d, Redwood City, Calif. Benjamin-Cummings, 1991, P. 94. With permission. c 2000 by CRC Press LLC
© 2000 by CRC Press LLC VBB = VTH = VCC (R1)/(R1 + R2) RB = RTH = R1//R2 For this biasing system, the Thévenin equivalent resistance and the Thévenin equivalent voltage can be determined. For design with the biasing system shown in Fig. 28.3, then: R1 = RB /(1 – VBB /VCC) R2 = RB (VC C /VBB) Graphical Approach To understand the graphical approach, a clear understanding of the dc and ac load lines is necessary. The dc load line is based on the Kirchhoff’s equation from the dc power source to ground (all capacitors open) VCC = vCE + iC RDC where RDC is the sum of the resistors in the collector-emitter loop. The ac load line is the loop, assuming the transistor is the ac source and the source voltage is zero, then V¢ CC = vce + iC Rac where Rac is the sum of series resistors in that loop with all the capacitors shorted. The load lines then can be constructed on the characteristic curves as shown in Fig. 28.5. From this it can be seen that to get the maximum output voltage swing, the quiescent point, or Q point, should be located in the middle of the ac load line. To place the Q point in the middle of the ac load line, ICQ can be determined from the equation ICQ = VCC /(RDC + Rac) FIGURE 28.5 Load lines. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 94. With permission.)
Extreme nonlinear region (saturation region) in middle of load line ct FIGURE 28.6 Q point in middle of load line. Source: C ] Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed,, Redwood City, Calif Benjamin-Cummings, 1991, P 135. With permission. To minimize distortion caused by the cutoff and saturation regions, the top 5%and the bottom 5% are discarded. This then results in the equation( Fig. 28.6 Vo(peak to peak)=2(0.9)IcQ(rc/R If, however, the Q point is not in the middle of the ac load line, the output voltage swing will be reduced. Below the middle of the ac load line[Fig. 28.7(a)] )=2(l-0.05Iox)Rc∥/R2 Above the middle of the ac load line [Fig. 28.7(b): Vo(peak to peak)=2(0.95 IoMax-Ico)Rc/RL These values allow the highest allowable input signal to be used to avoid any distortion by dividing the voltage gain of the amplifier into the maximum output voltage swing. The preceding equations are the same for the CB configuration For the EF configurations, the Rc is changed to Re in the equations ac load line elector load line (a)l below middle of ac load line (b)Ico above middle of ac load line FIGURE 28. 7 Reduced output voltage swing. (Source: C. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed, Redwood City, Calif Benjamin-Cummings, 1991, P. 136. With permission
© 2000 by CRC Press LLC To minimize distortion caused by the cutoff and saturation regions, the top 5% and the bottom 5% are discarded. This then results in the equation (Fig. 28.6): Vo (peak to peak) = 2 (0.9) ICQ (RC //RL) If, however, the Q point is not in the middle of the ac load line, the output voltage swing will be reduced. Below the middle of the ac load line [Fig. 28.7(a)]: Vo (peak to peak) = 2 (ICQ – 0.05 I CMax) RC //RL Above the middle of the ac load line [Fig. 28.7(b)]: Vo (peak to peak) = 2 (0.95 I CMax – ICQ) RC //RL These values allow the highest allowable input signal to be used to avoid any distortion by dividing the voltage gain of the amplifier into the maximum output voltage swing. The preceding equations are the same for the CB configuration. For the EF configurations, the RC is changed to RE in the equations. FIGURE 28.6 Q point in middle of load line. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 135. With permission.) FIGURE 28.7 Reduced output voltage swing. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 136. With permission.)