《电子工程师手册》学习资料（英文版）chapter 23 Semiconductor Manufacturing.pdf

23 Semiconductor Manufacturing 23.1 Processes Thermal Oxidation. Diffusion.lon Implantation.Deposition Harold g. Parks Lithography and Pattern Transfer The University of Arizona, Tucson 3.2 Testing Wayne Needham Built-In Self-Test.Scan Direct Access Testing. Joint Test Action Group. Pattern Generation for Functional Test Using Unit Delay. Pattern Generation for Timing. Temperature, Voltage, and S. Rajaram Processing Effects. Fault Grading. Test Program Flow Lucent Technologies 23.3 Electrical Characterization of Interconnections Interconnection Metrics Interconnection Electrical Parameters Conor Rafferty 23.4 Process Modeling and Simulation Bell laboratories. Lucent lon Implantation. Diffusion.Oxidation. Etching 23.1Pr Harold g. parks Integrated circuit(IC) fabrication consists of a sequence of processing steps referred to as unit step processes that result in the devices contained on todays microchips. These unit step processes provide the methodology for introducing and transporting dopants to change the conductivity of the semiconductor substrate, growing thermal oxides for inter-and intra-level isolation, depositing insulating and conducting films, and patterning and etching the various layers in the formation of the IC. Many of these unit steps have essentially remained the same since discrete component processing, whereas many have originated and grown with the integrated circuit evolution from small-scale integration(SSI) with less than 50 components per chip through very large scale integration(VLSI) with up to one million devices per chip. As the ultra large scale integration(ULSI) with more than a million devices per chip, proceeds to billion-device chips shortly after the turn of the entury, new processes and further modification of the current unit step processes will be required. In this section the unit step processes for silicon IC processing as they exist today with an eye toward the future are presented. How they are combined to form the actual IC process will be discussed in a later section. Due to space limitations only silicon processes are discussed. This author does not feel this is a major limitation, as many of the steps are used in processing other types of semiconductors, and perhaps more than 98% of all ICs today and in he near future are and will be silicon. Furthermore, only the highlights of the unit steps can be presented in this space, with ample references provided for a more thorough presentation. Specifically, the referenced processing textbooks provide detailed discussion of all processes. Thermal Oxidation Silicon dioxide(Sio, layers are important in integrated circuit technology for surface passivation, as a diffusion barrier and as a surface dielectric. The fact that silicon readily forms a high-quality, dense, natural oxide is the major reason it is the dominant integrated circuit technology today. If a silicon wafer is exposed to air, it will c 2000 by CRC Press LLC

© 2000 by CRC Press LLC 23 Semiconductor Manufacturing 23.1 Processes Thermal Oxidation • Diffusion • Ion Implantation • Deposition • Lithography and Pattern Transfer 23.2 Testing Built-In Self-Test • Scan • Direct Access Testing • Joint Test Action Group • Pattern Generation for Functional Test Using Unit Delay • Pattern Generation for Timing • Temperature, Voltage, and Processing Effects • Fault Grading • Test Program Flow 23.3 Electrical Characterization of Interconnections Interconnection Metrics • Interconnection Electrical Parameters 23.4 Process Modeling and Simulation Ion Implantation • Diffusion • Oxidation • Etching • Deposition • Lithography • Summary and Future Trends 23.1 Processes Harold G. Parks Integrated circuit (IC) fabrication consists of a sequence of processing steps referred to as unit step processes that result in the devices contained on today’s microchips. These unit step processes provide the methodology for introducing and transporting dopants to change the conductivity of the semiconductor substrate, growing thermal oxides for inter- and intra-level isolation, depositing insulating and conducting films, and patterning and etching the various layers in the formation of the IC. Many of these unit steps have essentially remained the same since discrete component processing, whereas many have originated and grown with the integrated circuit evolution from small-scale integration (SSI) with less than 50 components per chip through very large scale integration (VLSI) with up to one million devices per chip. As the ultra large scale integration (ULSI) era, with more than a million devices per chip, proceeds to billion-device chips shortly after the turn of the century, new processes and further modification of the current unit step processes will be required. In this section the unit step processes for silicon IC processing as they exist today with an eye toward the future are presented. How they are combined to form the actual IC process will be discussed in a later section. Due to space limitations only silicon processes are discussed. This author does not feel this is a major limitation, as many of the steps are used in processing other types of semiconductors, and perhaps more than 98% of all ICs today and in he near future are and will be silicon. Furthermore, only the highlights of the unit steps can be presented in this space, with ample references provided for a more thorough presentation. Specifically, the referenced processing textbooks provide detailed discussion of all processes. Thermal Oxidation Silicon dioxide (SiO2) layers are important in integrated circuit technology for surface passivation, as a diffusion barrier and as a surface dielectric. The fact that silicon readily forms a high-quality, dense, natural oxide is the major reason it is the dominant integrated circuit technology today. If a silicon wafer is exposed to air, it will Harold G. Parks The University of Arizona, Tucson Wayne Needham Intel Corporation S. Rajaram Lucent Technologies Conor Rafferty Bell Laboratories, Lucent Technology

grow a thin(=45 A)oxide in a relatively short time. To achieve the thicknesses of SiO2 used in integrated circuit hnology(100 A to 2 um)alternative steps must be taken. Thermal oxidation is an extension of the natural oxide growth at an elevated temperature( 800 to 1200oC). The temperature is usually selected out of compro- mise,i.e, it must be high enough to grow the oxide in a reasonable time and it must be as low as practical to minimize crystal damage and unwanted diffusion of dopants already in the wafer. The Oxidation process Thermal oxidation is usually accomplished by placing wafers in a slotted quartz carrier which is inserted into a quartz furnace tube. The tube is surrounded by a resistance heater and has provisions for controlled flow of an inert gas such as nitrogen and the oxidant. a vented cap is placed over the input end of the tube. The gas flows in the back end of the tube, over the wafers, and is exhausted through the vented cap. The wafer zone has a flat temperature profile to within 1/2C and can handle up to 50 parallel stacked wafers. Modern furnaces are computer controlled and programmable Wafers are usually loaded, in an inert environment, ramped to temperature, and switched to the oxidant for a programmed time. When the oxidation is complete the gas is switched back to the inert gas and the temperature is ramped down to the unload temperature. All these mplications in the process are to minimize thermal stress damage to the wafers and the procedures can vary onsiderably. Detailed discussions of the equipment and procedures can be found in references[Sze, 1983] The two most common oxidizing environments are dry and wet. As the name implies, dry oxides are grown in dry O2 gas following the reaction Si+o et oxides were originally grown by bubbling the dry oxygen gas through water at 95C. Most"wet"oxides today are accomplished by the pyrogenic reaction of H, and o, gas to form steam, and are referred to as steam oxidations. In either case the reaction is essentially the same at the wafer: Si+H2O→SiO2+2H2 (23.2) The oxidation process can be modeled as shown in Fig. 23. 1 The position Xo represents the Si/SiO, interface which is a moving Oxide Silicon boundary. The volume density of oxidizing species in the bulk NG gas, N, is depleted at the oxide surface, Ns, due to an amount, No, being incorporated in the oxide layer. The oxidizing species then diffuses across the growing oxide layer where it reacts with the silicon at the moving interface to form SiO,. FG represents the flux of oxidant transported by diffusion from the bulk gas to the oxide surface. The oxidizing species that enters the Sio iffuses across the growing SiO, layer with a flux, For. A reaction takes place at the Si/SiO, interface that consumes some or all of NI the oxidizing species, as represented by the flux, Fr. In steady state these three flux terms are equal and can be used to solve for the concentrations N, and No in terms of the reaction rate and diffusion coefficient of the oxidizing species This in turn specifies the flux terms which can be used in the FIGURE 23. 1 Model of the oxidation process solution of the differential equation dx F for the oxide growth, x In this equation No is the number of oxidant molecules per unit volume of oxide. An excellent derivation of the growth equation is given in Grove [1967]. Here we give the result which can be c 2000 by CRC Press LLC

© 2000 by CRC Press LLC grow a thin (≈45 Å) oxide in a relatively short time. To achieve the thicknesses of SiO2 used in integrated circuit technology (100 Å to 2 µm) alternative steps must be taken. Thermal oxidation is an extension of the natural oxide growth at an elevated temperature (800 to 1200°C). The temperature is usually selected out of compromise, i.e., it must be high enough to grow the oxide in a reasonable time and it must be as low as practical to minimize crystal damage and unwanted diffusion of dopants already in the wafer. The Oxidation Process Thermal oxidation is usually accomplished by placing wafers in a slotted quartz carrier which is inserted into a quartz furnace tube. The tube is surrounded by a resistance heater and has provisions for controlled flow of an inert gas such as nitrogen and the oxidant. A vented cap is placed over the input end of the tube. The gas flows in the back end of the tube, over the wafers, and is exhausted through the vented cap. The wafer zone has a flat temperature profile to within 1/2°C and can handle up to 50 parallel stacked wafers. Modern furnaces are computer controlled and programmable. Wafers are usually loaded, in an inert environment, ramped to temperature, and switched to the oxidant for a programmed time. When the oxidation is complete the gas is switched back to the inert gas and the temperature is ramped down to the unload temperature. All these complications in the process are to minimize thermal stress damage to the wafers and the procedures can vary considerably. Detailed discussions of the equipment and procedures can be found in references [Sze, 1983]. The two most common oxidizing environments are dry and wet. As the name implies, dry oxides are grown in dry O2 gas following the reaction: Si + O2 → SiO2 (23.1) Wet oxides were originally grown by bubbling the dry oxygen gas through water at 95°C. Most “wet” oxides today are accomplished by the pyrogenic reaction of H2 and O2 gas to form steam, and are referred to as steam oxidations. In either case the reaction is essentially the same at the wafer: Si + H2O → SiO2 + 2H2 (23.2) The oxidation process can be modeled as shown in Fig. 23.1 The position X0 represents the Si/SiO2 interface which is a moving boundary. The volume density of oxidizing species in the bulk gas, NG, is depleted at the oxide surface, NS, due to an amount, N0, being incorporated in the oxide layer. The oxidizing species then diffuses across the growing oxide layer where it reacts with the silicon at the moving interface to form SiO2. FG represents the flux of oxidant transported by diffusion from the bulk gas to the oxide surface. The oxidizing species that enters the SiO2 diffuses across the growing SiO2 layer with a flux, Fox. A reaction takes place at the Si/SiO2 interface that consumes some or all of the oxidizing species, as represented by the flux, FI. In steady state these three flux terms are equal and can be used to solve for the concentrations NI and N0 in terms of the reaction rate and diffusion coefficient of the oxidizing species. This in turn specifies the flux terms which can be used in the solution of the differential equation: (23.3) for the oxide growth, x. In this equation Nox is the number of oxidant molecules per unit volume of oxide. An excellent derivation of the growth equation is given in Grove [1967]. Here we give the result which can be represented by: FIGURE 23.1 Model of the oxidation process. dx dt F Nox =

Oxidation rate depends on substrate orientation [Ghandhi, 1968]. This effect is related to the surf density of the substrate, i. e,, the higher the density, the faster the oxidation rate. Oxidation rate also on pressure. The linear and parabolic rates are dependent on the equilibrium concentration of the species in the SiO2 which is directly proportional to the partial pressure of the oxidant in the ambient. Oxide growth rate shows a doping dependence for heavily doped substrates(>102 cm-). Boron increases the parabolic rate constant and phosphorus enhances the linear rate constant Wolf and Tauber, 1986 Oxide Characteristics Dry oxides grow more slowly than wet oxides, resulting in higher density, higher breakdown field strengths, and more controlled growth, making them ideal for metal-oxide semiconductor(MOS)gate dielectrics Wet oxidation is used for forming thick oxides for field isolation and masking implants and diffusions. The slight degradation in oxide density is more than compensated for by the thickness in these application <100> substrates have fewer dangling bonds at the surface, which results in lower fixed oxide charge and interface traps and therefore higher quality MOS devices. Conventional dopants(B, P, As, and Sb)diffuse slowly in both wet ai oxides and hence these oxides provide a good barrier for masking diffusions in integrated circuit fabrication High-pressure steam oxidations provide a means for growing relatively thick oxides in reasonable times at low temperatures to avoid dopant diffusion. Conversely, low-pressure oxidations show promise for forming controlled ultra thin gate growth for ULSI technologies. Chlorine added to gate oxides [Sze, 1988] has been shown to reduce mobile ions, reduce oxide defects, increase breakdown voltage, reduce fixed oxide charge and interface traps, reduce oxygen-induced stacking faults, and increase substrate minority carrier lifetime. Chlorine is introduced into dry oxidations in less tha 5%concentrations as anhydrous HCl gas or by trichloroethylene(TCE)or trichloroethane(TCA) Dopant Segregation and Redistribution Since silicon is consumed during the oxidation process, the dopant in the substrate will redistribute due to segregation[ Wolf and Tauber, 1986]. The boundary condition across the Si/SiO2 interface is that the chemical potential of the dopant is the same on both sides. This results in the definition of a segregation coefficient, m, as the ratio of the equilibrium concentration of dopant in Si to SiO. Depending on the value of m(i. e, less than or greater than 1)and the diffusion properties of the dopant SiO,, various redistributions are possible. For example, m=0. for boron and it is a slow diffuser in Sio2 o it tends to deplete from the Si surface and accumulate in the oxide at the Si/Sio2 interface. Phosphorus, on the other hand, has m=10, is also a slow diffuser in SiO2, and tends to pile up in the Si at the Si/Sio2 interface Antimony and arsenic behave similarly to phosphorus Diffusion Diffusion was the traditional way dopants were introduced into silicon wafers to create junctions and control the resistivity of layers. Ion implantation has now superseded diffusion for this purpose. The principles and concepts of diffusion theory, however, remain important since they describe the movement and transport of dopants and impurities during the high-temperature processing steps of integrated circuit manufacture. Diffusion mechanism Consider a silicon wafer with a high concentration of an impurity on its surface. At any temperature there ar a certain number of vacancies in the Si lattice. If the wafer is subjected to an elevated temperature, the number of vacancies in the silicon will increase and the impurity will enter the wafer moving from the high surface concentration to redistribute in the bulk. The redistribution mechanism is diffusion, and dependi impurity type it will either be substitutional or interstitial [Ghandhi, 1982] For substitutional diffusion the impurity atom substitutes for a silicon atom at a vacancy lattice site and then progresses into the wafer by hopping from lattice site to lattice site via the vacancies. Clearly, the hopping can e in a random direction; however, since the impurity is present initially in high concentration on the surface only, there is a net flow of the impurity from the surface into the bulk, c2000 by CRC Press LLC

© 2000 by CRC Press LLC Oxidation rate depends on substrate orientation [Ghandhi, 1968]. This effect is related to the surface atom density of the substrate, i.e., the higher the density, the faster the oxidation rate. Oxidation rate also depends on pressure. The linear and parabolic rates are dependent on the equilibrium concentration of the oxidizing species in the SiO2 which is directly proportional to the partial pressure of the oxidant in the ambient. Oxide growth rate shows a doping dependence for heavily doped substrates (>1020 cm–3). Boron increases the parabolic rate constant and phosphorus enhances the linear rate constant [Wolf and Tauber, 1986]. Oxide Characteristics Dry oxides grow more slowly than wet oxides, resulting in higher density, higher breakdown field strengths, and more controlled growth, making them ideal for metal-oxide semiconductor (MOS) gate dielectrics. Wet oxidation is used for forming thick oxides for field isolation and masking implants and diffusions. The slight degradation in oxide density is more than compensated for by the thickness in these applications. <100> substrates have fewer dangling bonds at the surface, which results in lower fixed oxide charge and interface traps and therefore higher quality MOS devices. Conventional dopants (B, P, As, and Sb) diffuse slowly in both wet and dry oxides and hence these oxides provide a good barrier for masking diffusions in integrated circuit fabrication. High-pressure steam oxidations provide a means for growing relatively thick oxides in reasonable times at low temperatures to avoid dopant diffusion. Conversely, low-pressure oxidations show promise for forming controlled ultra thin gate growth for ULSI technologies. Chlorine added to gate oxides [Sze, 1988] has been shown to reduce mobile ions, reduce oxide defects, increase breakdown voltage, reduce fixed oxide charge and interface traps, reduce oxygen- induced stacking faults, and increase substrate minority carrier lifetime. Chlorine is introduced into dry oxidations in less than 5% concentrations as anhydrous HCl gas or by trichloroethylene (TCE) or trichloroethane (TCA). Dopant Segregation and Redistribution Since silicon is consumed during the oxidation process, the dopant in the substrate will redistribute due to segregation [Wolf and Tauber, 1986]. The boundary condition across the Si/SiO2 interface is that the chemical potential of the dopant is the same on both sides. This results in the definition of a segregation coefficient, m, as the ratio of the equilibrium concentration of dopant in Si to the equilibrium concentration of dopant in SiO2. Depending on the value of m (i.e., less than or greater than 1) and the diffusion properties of the dopant in SiO2, various redistributions are possible. For example, m ª 0.3 for boron and it is a slow diffuser in SiO2, so it tends to deplete from the Si surface and accumulate in the oxide at the Si/SiO2 interface. Phosphorus, on the other hand, has m ª 10, is also a slow diffuser in SiO2, and tends to pile up in the Si at the Si/SiO2 interface. Antimony and arsenic behave similarly to phosphorus. Diffusion Diffusion was the traditional way dopants were introduced into silicon wafers to create junctions and control the resistivity of layers. Ion implantation has now superseded diffusion for this purpose. The principles and concepts of diffusion theory, however, remain important since they describe the movement and transport of dopants and impurities during the high-temperature processing steps of integrated circuit manufacture. Diffusion Mechanism Consider a silicon wafer with a high concentration of an impurity on its surface. At any temperature there are a certain number of vacancies in the Si lattice. If the wafer is subjected to an elevated temperature, the number of vacancies in the silicon will increase and the impurity will enter the wafer moving from the high surface concentration to redistribute in the bulk. The redistribution mechanism is diffusion, and depending on the impurity type it will either be substitutional or interstitial [Ghandhi, 1982]. For substitutional diffusion the impurity atom substitutes for a silicon atom at a vacancy lattice site and then progresses into the wafer by hopping from lattice site to lattice site via the vacancies. Clearly, the hopping can be in a random direction; however, since the impurity is present initially in high concentration on the surface only, there is a net flow of the impurity from the surface into the bulk