Physical Structure-3 N-wells allow both NMOS and PMOS devices to reside on the same piece of die. n-substrate (a) p-substrate (h) As mentioned,NMOS and PMOS devices have 4 terminals: Source,Drain,Gate,Substrate (bulk) In order to have all PN junctions reverse-biased,substrate of NMOS is connected to the most negative voltage,and substrate of PMOS is connected to the most positive voltage. 4西/d 6
2020/3/7 6 SM 15 EECE 488 ± Set 1: Introduction and Background Physical Structure - 3 N-wells allow both NMOS and PMOS devices to reside on the same piece of die. As mentioned, NMOS and PMOS devices have 4 terminals: Source, Drain, Gate, Substrate (bulk) In order to have all PN junctions reverse-biased, substrate of NMOS is connected to the most negative voltage, and substrate of PMOS is connected to the most positive voltage
Physical Structure -4 MOS transistor Symbols: NMOS PMOS NMOS PMOS NMOS PMOS D D D Go- …0B (a) (b) (e】 。In NMOS Devices:Source-cleciron→Drain Current flows from Drain to Source ·In PMOS Devices:Source-_hoe→Drain Current flows from Source to Drain 。 Current flow determines which terminal is Source and which one is Drain.Equivalently,source and drain can be determined based on their relative voltages. 西/
2020/3/7 7 SM 16 EECE 488 ± Set 1: Introduction and Background Physical Structure - 4 MOS transistor Symbols: In NMOS Devices: Current flows from Drain to Source In PMOS Devices: Current flows from Source to Drain Current flow determines which terminal is Source and which one is Drain. Equivalently, source and drain can be determined based on their relative voltages. Source Drain electron o Source Drain hole o
Threshold Voltage -1 Consider an NMOS:as the gate voltage is increased,the surface under the gate is depleted.If the gate voltage increases more, free electrons appear under the gate and a conductive channel is formed. 40.1V 40.1V +0.1V n p-substrate p-substrate Negative lons b +0.1V +0.1V p-substrate p-substrate Electrons c (a)An NMOS driven by a gate voltage,(b)formation of depletion region,(c)onset of inversion, and(d)channel formation As mentioned before,in NMOS devices charge carriers in the channel under the gate are electrons. 2西7
2020/3/7 8 SM 17 EECE 488 ± Set 1: Introduction and Background Threshold Voltage - 1 (a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion, and (d) channel formation Consider an NMOS: as the gate voltage is increased, the surface under the gate is depleted. If the gate voltage increases more, free electrons appear under the gate and a conductive channel is formed. As mentioned before, in NMOS devices charge carriers in the channel under the gate are electrons
Threshold Voltage -2 Intuitively,the threshold voltage is the gate voltage that forces the interface(surface under the gate)to be completely depleted of charge (in NMOS the interface is as much n-type as the substrate is p-type) Increasing gate voltage above this threshold (denoted by VTH or V) induces an inversion layer(conductive channel)under the gate. Gate electrode Induced G n-type D Oxide (SiO,) channel p-type substrate Depletion region 专 Microelectronic Circuits,2004 Oxford University Press 心2西月日
2020/3/7 9 SM 18 EECE 488 ± Set 1: Introduction and Background Threshold Voltage - 2 Intuitively, the threshold voltage is the gate voltage that forces the interface (surface under the gate) to be completely depleted of charge (in NMOS the interface is as much n-type as the substrate is p-type) Increasing gate voltage above this threshold (denoted by VTH or Vt ) induces an inversion layer (conductive channel) under the gate. © Microelectronic Circuits, 2004 Oxford University Press
Threshold Voltage -3 Analytically: %m=s+2-m+2 Where: ΦMs=Built-in Potential=Φgate-Silicon the difference between the work functions of the polysilico n gate and the silicon substrate Work Function (electrostaticpotentiai)-K n. Qn=Charge in the depletion region=V4:q:s。·Φ，N 西/司 10
2020/3/7 10 SM 19 EECE 488 ± Set 1: Introduction and Background Threshold Voltage - 3 Analytically: ox dep TH MS F C Q V ) 2 ) Where: the polysilicon gate and the silicon substrate the difference between the work functions of Built -inPotential )MS )gate )Silicon ¸ ¸ ¹ · ¨ ¨ © § ) i sub F n N q K T Work Function (electrostatic potential) ln Qdep q si F Nsub Charge in the depletion region 4 H )